In recent years, data traffic mainly based on use of Internet has been abruptly increasing. There is also a move afoot to do, on the Internet, highly reliable service of high quality such as transaction processing which has conventionally been performed using a leased line. In order to cope with this, it is required to meet the tendency of not only a transmission path, but also the packet data communication device with larger capacity, higher speed and higher reliability. Further, in order to cope with a new routing protocol or a new service quickly in the future, or in order to make it possible to simply add a necessary function, the flexibility of adding a function is requested for the packet data communication device.
For example, a router device performs layer 3 processing as a packet data communication device. Particularly, many high-performance router devices enable high performance routing and forwarding with hardware. The structure of a hardware router has been disclosed in Non-patent Literature 1, for example.
FIG. 12 shows an outline of a hardware router disclosed in the Non-Patent Literature 1. A plurality of routing processors 801 each having a network interface 811 are connected to each other through a crossbar switch 800. Each routing processor 801 is composed of: a forwarding controller 812; a routine processor 813; a routing table 814; and a packet buffer 815. A header of an incoming packet from the network interface 811 is extracted by the forwarding controller 812, and the route is retrieved by hardware in the routing processor 813. In the routing table 814, output destination information corresponding to a destination IP address, security-oriented filtering information and information of QoS (Quality of Service) are stored beforehand. The IP packet, search processing of which has been completed, is inputted into the packet buffer 815, and after arbitration for output among other routing processors 801 is performed, is transferred to a desired output port through the crossbar switch 800. The routing manager 802 deals with a routing protocol, which transmits and receives routing information to or from other routers connected thereto to determine a forwarding path of each IP packet. The forwarding path thus determined is reflected to the routing table 814 within the routing processor 801. As described above, this is constructed such that the routine processors and the packet buffers are separated.
Another example of the structure of hardware router is disclosed in a Patent Literature 1.
FIG. 13 shows an outline of a hardware router disclosed in the Patent Literature 1. An incoming IP packet through an input port 901 is stored in a buffer memory 903 through an input switch 902. In the input switch 902, KEY information 904, such as a destination IP address in the IP packet, is read out and transferred to a controller 905. In the controller 905, after destination search processing for each packet is performed, this result (RESULT 906) is transmitted to an output switch 907. In the output switch 907, the IP packet stored in a buffer memory 903 is read out on the output port 908 according to the RESULT 906. As described above, this is constructed such that the routing processor and the packet buffer are centralized.
Furthermore, in a Patent Literature 2, there has been disclosed a hardware router in which a labeling packet and the IP packet are judged by an input line interface, and the IP header is transmitted to a forwarding engine for being processed according to the judgment result. However, no consideration has been given to scalability or extensibility of the processing.
[Non-Patent Literature 1]
Itaru Mimura and two others, “Terabit Node for Next-generation IP Networks”, [online], December 2000, HITACHI REVIEW, retrieved on Jan. 30, 2003, Internet.
[Patent Literature 1]
U.S. Pat. No. 5,905,725
[Patent Literature 2]
JP-A No. 64542/2002
The switch shown in the Non-Patent Literature 1 is comparatively high in scalability in processing capacity because the routing function and the forwarding function are separated. In the structure shown in the Non-Patent Literature 1, however, the forwarding controller and the routing controller are tightly coupled and are mounted on the same routing processor. When it is considered that these are implemented with hardware, in order to cope with new routing protocol or a new service quickly, the whole hardware needs to be modified. In other words, the structure is not suitable for adding new function easily.
Also, the switch disclosed in the Patent Literature 1 has good efficiency of buffer memory usage, because the routing function and the forwarding function are centralized, and has a feature that the device can be downsized. However, it is difficult to scale up this structure, because processing of the routing function and the forwarding function is prone to become a bottleneck of the system. Therefore the structure is inferior in terms of performance scalability. The routing function and the forwarding function are separated in this system and in order to, for example, cope with new protocol, it is required to remake the routing hardware. Therefore it does not have flexibility in adding a function. Besides, this system does not have a structure in which any application layer services can be added as needed.